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Advances in quantum computing have urged the need for cryptographic algorithms that are low-power, low-energy, and secure against attacks that can be potentially enabled. For this post-quantum age, different solutions have been studied. Code-based cryptography is one feasible solution whose hardware architectures have become the focus of research in the NIST standardization process and has been advanced to the final round (to be concluded by 2022–2024). Nevertheless, although these constructions, e.g., McEliece and Niederreiter public key cryptography, have strong error correction properties, previous studies have proved the vulnerability of their hardware implementations against faults product of the environment and intentional faults, i.e., differential fault analysis. It is previously shown that depending on the codes used, i.e., classical or reduced (using either quasi-dyadic Goppa codes or quasi-cyclic alternant codes), flaws in error detection could be observed. In this work, efficient fault detection constructions are proposed for the first time to account for such shortcomings. Such schemes are based on regular parity, interleaved parity, and two different cyclic redundancy checks (CRC), i.e., CRC-2 and CRC-8. Without losing the generality, we experiment on the McEliece variant, noting that the presented schemes can be used for other code-based cryptosystems. We perform error detection capability assessments and implementations on field-programmable gate array Kintex-7 device xc7k70tfbv676-1 to verify the practicality of the presented approaches. To demonstrate the appropriateness for constrained embedded systems, the performance degradation and overheads of the presented schemes are assessed. 

Practical, hands-on hardware experience is an essential component of computer engineering education. Due to the COVID-19 pandemic, courses with laboratory components such as Computer Logic Design or FPGA Design were subject to interruption from sudden changes in course modality. While simulators can cover some aspects of laboratory work, they cannot fully replace the hands-on experience students receive working with and debugging hardware. For hardware security in particular, experimenting with attacks and countermeasures on real hardware is vital. In this paper, we describe our approach to designing a practical, hands-on hardware security course that is suitable for HyFlex delivery. We have developed a total of nine experiments utilizing two inexpensive, portable, and self--contained development boards which generally obviate the need for bench equipment. We discuss the trade-offs inherent in the course and experiment design, as well as issues relating to deployment and support for the required design software.